Memory devices can store data values for access by other devices of a system. To increase overall access speeds from some applications, data locations can be accessed in a sequential fashion, often referred to as a “burst” access. In one conventional approach, a memory device can have a burst length set by a user or hardwired into device. In a burst access operation (e.g., read or write), an initial address can be provided to the memory device. In response, the memory device can access the initial address, and a follow sequence of addresses up to the burst length. Address progression can be according to various counting conventions, including linear and interleaved.
Provided a burst access begins and ends within a same row of a memory cell array, such an access introduces essentially no change in latency between data values accessed (access is “at speed”). However, if a burst access spans rows, delays may be introduced. To better understand features of the disclosed embodiments, a conventional memory device and burst will now be described with reference to FIGS. 19 and 20.
FIG. 19 shows a conventional arrangement in which a burst access across rows can introduce a latency into data access speeds. FIG. 19(a) illustrates how a burst access can have a base address BASE ADD which indicates a first data location of a burst access, as well as one or more burst addresses BURST ADDS that follow the base address. As shown in FIG. 19(a), a burst sequence crosses a row boundary, with part of the burst sequence accessing a row (ROWn) and the remainder of the burst sequence accessing the next row (ROW(n+1)).
FIGS. 19(b) to 19(e) show how latency can be introduced into the burst access illustrated by FIG. 19(a). Referring to FIG. 19(b), at the start of the burst access, a word line WLn can be activated that corresponds to ROWn. As shown in FIG. 19(c), data locations can then be accessed for those portions of the burst directed to ROWn.
However, after ROWn is accessed, a memory device will cycle through access operations (precharge, decode, etc.). After some delay, as shown in FIG. 19(d), a next word line WL(n+1) corresponding to ROW(n+1) can be activated. Such data for this next row can then be accessed, as shown in FIG. 19(e).
FIG. 20 is a timing diagram showing the latency effect for a burst write operation that crosses physical rows. At time t0 a first data value (Dn) of a burst sequence can be input. This data value can be a last data value of an initial row. At time t1, a next data value (D(n+1)) of the burst sequence is input. However, this data value corresponds to a first data location of a next row. Consequently, a burst sequence must stop as access is switched from an initial row to the next row. Once access to the next row is established, a burst access can resume at time t2 with the writing of data value D(n+2).